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This tutorial demonstrates how to add and modify peripherals to an existing MicroBlaze system using Xilinx Platform Studio (XPS). The system from the previous tutorial will be used as the starting point. We will follow the instructions from the "Introduction to MicroBlaze Hardware Development Lab 2". The tutorial will show:
How to add an EDK peripheral
How to connect to the existing system
How to modify the peripheral options
How to add constraints for the new peripheral
This is what our embedded system looks like. We will add a General Purpose IO (GPIO) core to make use of the DIP switches on the board.
We will do all the hardware design implementation in XPS and all software writing in SDK. From now on we skip ISE to make things easier.
Finding and adding an EDK IP
In XPS click the IP Catalog tab to display all available IPs provided by Xilinx. Open up the General Purpose IO and select AXI General Purpose IO 1.01a. Right-click the entry and chose Add IP.
The peripheral configuration window will open automatically. Select Channel 1 and change the GPIO Data Channel Width from 32 to 4. Change Channel 1 is Input Only from 0 to 1.
The peripheral is connect to the MicroBlaze core.
In the System Assembly click on the axi_gpio_0 and rename it to DIP_Switches.
Click on the Address tab to display this window. The addresses view shows the address space for all peripherals. The Lock box prevents the address for that peripheral from being changed when generating new addresses.
Click on the Generate Addresses button to generate the address range for the new GPIO peripheral.
To view the datasheet for the GPIO interface right-click the AXI General Purpose IO entry in the IP Catalog and select <View PDF Datasheet>. Here is the schematics taken from the datasheet.
Click on the ports tab. The Ports view shows the internal connections between the peripherals as well as the external ports. Expand the DIP_Switches. It will show the connections available for the peripheral.
Expand the (IO_IF) gpio_O selection.
Select the GPIO_IO_I since the DIP switches are only inputs.
Click on <No Connection> drop-down list in the Net column.
Select <Make External> to add the port to the external port list.
Select GPIO_IO net and set <No Connection>.
Modifying the UCF file
The User Constraint File (UCF) holds design constraints for external input and output pins in our design. It was generated automatically when we generated our hardware design the first time. After adding an IP core manually we have to manually enter constraints for new external ports. The ucf file can be found in the project sub directory called data.
To edit the UCF file double-click the UCF File entry in the Project Files window and add the following lines:
These pins are hardwired to the DIP switches.
Generate new netlist and bitstream
Select Hardware->Generate Netlist to generate a new netlist. Select hardware->Generate Bitstream to generate a new bitstream.
Adding a standard Xilinx IP core is a simple task if you know how to do it.