New Horizons









Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.



Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

Linux
Installing Cobra Command Tool
A processor benchmark

Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Bicycling
Stockholm by bike

Running
The New York City Marathon

Skiing/Skating
Kittelfjall Lappland

Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Monday, September 19, 2011
FPGA design from scratch. Part 66
Using the Software Development Kit

To start a software project in SDK, the hardware design information needs to be exported from XPS to SDK. Go to Project->Export Hardware Design to SDK.



Include the bitstream and BMM files and click Export Only.The exported files are located in the SDK/SDK_Export/hw directory inside the XPS project directory.

When finished we are ready to start SDK.

--> xsdk &

We will use the SDK directory as our workspace.



SDK will open and display the Welcome page.


Getting help

To get help select Help->Help Content to display this page.



Before we start

We have to make sure
gmake is installed. If we are using Ubuntu gmake is named make. Here is an easy fix, adding a soft link to the make program:

sudo ln -s /usr/bin/make /usr/bin/gmake


Starting a new C-project

Select File->New->Xilinx C Project to start. The first time we we start SDK after exporting our design, this window will be displayed. We have to move the hardware platform into the workspace.



Click Specify.



We have to specify the path to the LX9_AXI_system.xml file in the SDK_Export/hw directory. Now we are ready to start our software project.




We will use one of the project templates available, the Peripheral Tests and create a board support package (BSP) called Standalone_BSP.




Click Finish. The application will start building and create an ELF file, which is the compiled application. The SDK Project Navigator shows all the files generated during this process.




The main source file is called testperiph.c and looks like this.





Generate a linker script

The system contains internal BRAM memory as well as external DDR memory. We can select where the code will be physically located through a linker script. Right-click on the peripheral_tests_0 project and select Generate Linker Script. We will put the application code in LPDDR memory.



Program the FPGA

When programming the FPGA the hardware will be constructed and the memories will be loaded with the boot loader and application code.


 

Click the Program FPGA button  and specify the bitstream file (system.bit)  and the block memory map file (system_bd.bmm). SDK automatically detects the processor in the system and shows them in a table at the bottom of the window. Under Software Configuration, select the executable (.elf) file to initialize at the reset start address for the processor. This is the program the processor will start executing when it comes out of reset. We will use BootLoop.



Click Program to start the FPGA programming. Here is the console output from this action. The
data2mem program will build the complete programming file called download.bit which will be used to program the FPGA.




Setting up a run configuration

The FPGA is configured, the application program is loaded and we are ready to run. Right-click the Peripheral_test_0 entry in the Project Explorer and select Run As->Run Configuration. Select Xilinx C/C++ ELF and press the New button to create a run configuration of that type.



Select the STDIO Connection tab and mark the Connect STDIO to Console check box. Select port /dev/ttyUSB0 and leave the baud rate at 9600.




Click the RUN button to start program execution. Here is the printout on the console.



Congratulations!! We have our first program running.


Top Previous  Next


Posted at 13:26 by

Kursad Gol
March 4, 2012   09:43 PM PST
 
Hi Mr. Sven,

I still i have a problem. When I do “Export hardware design to SDK with bitstream” and after this i did “Program FPGA” on SDK v13.2 for lwip application, I have my_project.bit files 333 KB and microblaze_0.elf 1KB. I am sure i couldn’t create the right download.bit file. Because these files are dummy files. What will be the problem? And also i have too many warnings on my generation bit file. ISE v13.2 Design Summary says that “No errors and 284 warnings” Is this can be the problem? My computer’s Operating System is Windows XP Pro 2002 with Service Pack 3.

Thank you very much indeed.
 

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