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It can be hard to find all the available IP cores and their documentation. The easiest way is to look in the pcores directory in the Xilinx EDK installation.
Use this command to find out where the EDK installation is: echo $XILINX_EDK
We will look for the IP core plbv46_slave_single.
Here is what the directory structure looks like for an IP core. The doc directory contains the data sheet in pdf format.
The PLBV46 slave interface The plbv46_slave_single is designed to provide a user with a quick way to implement a light weight interface between the IBM PLB Bus and a user IP core. This slave service allows for multiple user IP's to be interfaced to the PLB bus providing address decoding over various address ranges as configured by the user. Optionally the plbv46_slave_single can be optimized for a point to point connection reducing FPGA resources and improving latency.
Instantiate the ETC block
We are not going to use the user_logic block instead we instantiate the ETC block directly in the etc_if entity. We will add all the PLB to OCB conversion code in the etc_if block when we have the test bench ready. For now we leave this code open (ipif_NC).
Importing an existing peripheral block
After adding the ETC block to our peripheral block we are ready to import it to our ETC system design. From the Hardware menu in XPS select <Create or Import Peripheral>.
We update the design to etc_if_v2.00
And find all design files and libraries that make up our design.
After going through a few more steps we are ready to import the peripheral to the ETC system.
Here are all the imported design files.
We now have a complete system. To make sure everything is connected we will run a trial synthesis. From the Hardware menu select <Generate Netlist> to start the synthesis. Fix all synthesis errors before proceeding to the next step.
Now we need some simple programs executed in the MicroBlaze processor that will write to and read from the peripheral. Time to start looking at SDK.