The Spartan-6 FPGA
We have finished the first phase of our FPGA project and we managed to fit the design in the Spartan-6 FPGA on the LX9 MicroBoard. Let's take a closer look at the FPGA device itself and try to understand how we can build our system using the logic in the FPGA. We will use the information we get from PlanAhead when we enter Design Analysis.
The Spartan-6 product specification
The Spartan-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity.
Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input look- up table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO technology, power-optimized high-speed serial transceiver blocks, PCI Express compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection.
Spartan-6 XC6SLX9
The FPGA device on the LX9 MicroBoard is the XC6SLX9. Here is the LX9_LXN_system implementation device view taken from PlanAhead:
Memory Controller Block
The MCB is a dedicated embedded block multi-port memory controller that greatly simplifies the task of interfacing Spartan-6 devices to the most popular memory standards. The MCB provides significantly higher performance, reduced power consumption, and faster development times than equivalent IP implementations. The embedded block implementation of the MCB conserves valuable FPGA resources and allows the user to focus on the more unique features of the FPGA design. Here is a block diagram showing the content of the MCB. The IP wrapper can be generated using the Core Generator. For more information see the Xilinx UG416 Spartan-6 FPGA Memory Interface Solutions.
The EDK library has a pre-configured memory controller called MCB3_LPDDR which we have used in our design.
The DSP48A1 DSP element
The DSP48A1 slice the digital signal processing (DSP) element in Spartan®-6 FPGAs. Each DSP48A1 slice forms the basis of a versatile, coarse-grained DSP architecture. The DSP48A1 slices support many independent functions, including multiplier, multiplier-accumulator (MACC), pre-adder/subtracter followed by a multiply-accumulator, multiplier followed by an adder, wide bus multiplexers, magnitude comparator, or wide counter. The architecture also supports connecting multiple DSP48A1 slices to form wide math functions, DSP filters, and complex arithmetic without the use of general FPGA logic. Here is the user guide..
DSP48A1 slice in detail
The BRAM block
The block RAM in Spartan-6 FPGAs stores up to 18K bits of data and can be configured as either two independent 9 Kb RAMs, or one 18 Kb RAM. Each RAM can be addressed through two ports, but can also be configured as a single-port RAM. The block RAM resources include output registers to increase pipeline performance. Block RAMs are placed in columns. The total number of block RAMs depends on the size of the Spartan-6 device.
Similar to other Xilinx FPGA block RAMs, Write and Read are synchronous operations; the two ports are symmetrical and totally independent, sharing only the stored data. Each port can be configured in one of the available widths, independent of the other port. The memory content can be initialized or cleared by the configuration bitstream. During a write operation the memory can be set to have the data output either remain unchanged, reflect the new data being written or the previous data now being overwritten. Embedded dual- or single-port RAM modules, ROM modules, synchronous FIFOs, and data-width converters are easily implemented using the Xilinx CORE Generator block memory modules. Dual-clock FIFOs can be generated using the CORE Generator FIFO Generator module.
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. The BRAM Block structural HDL is generated by the EDK design tools based on the configuration of the BRAM interface controller IP. All BRAM Block parameters are automatically calculated and assigned by the Platgen and Simgen EDK tools. More information can found in the user guide.
Clock Management Tiles
The Spartan-6 FPGA Clock Management Tiles (CMTs) provide very flexible, high-performance clocking. The Spartan-6 FPGA CMT blocks are located in the center column along the vertical global clock tree. Each CMT block contains two DCMs and one PLL. For more information see the user guide.
Phase Lock Loop (PLL)
The main purpose of PLLs is to serve as a frequency synthesizer for a wide range of frequencies, and to serve as a jitter filter for either external or internal clocks in conjunction with the DCMs of the CMT. The PLL block diagram shown in the figure provides a general overview of the PLL components.
Input MUXes select the reference and feedback clocks from either the IBUFG, BUFG, IBUF, PLL outputs, or one of the DCMs. Each clock input has a programmable counter D. The Phase-Frequency Detector (PFD) compares both phase and frequency of the input (reference) clock and the feedback clock. Only the rising edges are considered because as long as a minimum High/Low pulse is maintained, the duty cycle is not important.
The PFD is used to generate a signal proportional to the phase and frequency between the two clocks. This signal drives the Charge Pump (CP) and Loop Filter (LF) to generate a reference voltage to the Voltage Controlled Oscillator (VCO). The PFD produces an up or down signal to the charge pump and loop filter to determine whether the VCO should operate at a higher or lower frequency.
When VCO operates at too high of a frequency, the PFD activates a down signal, causing the control voltage to be reduced, which decreases the VCO operating frequency. When the VCO operates at too low of a frequency, an up signal will increase voltage. The VCO produces eight output phases. Each output phase can be selected as the reference clock to the output counters. Each counter can be independently programmed for a given customer design. A special counter, M, is also provided. This counter controls the feedback clock of the PLL allowing a wide range of frequency synthesis.
Digital Clock Managers
Digital Clock Managers (DCMs) provide advanced clocking capabilities to Spartan-6 FPGA applications. Primarily, DCMs eliminate clock skew, thereby improving system performance. Similarly, a DCM optionally phase shifts the clock output to delay the incoming clock by a fraction of the clock period. DCMs optionally multiply or divide the incoming clock frequency to synthesize a new clock frequency. The DCMs integrate directly with the global low-skew clock distribution network.
Open implemented design
In PlanAhead select <Open Implemented Design> from the <Implemented Design> menu.
Zooming in
To zoom in press the left mouse button and drag the cursor from upper right corner to the lower left corner.
Slice description
Every slice contains four logic-function generators (or look-up tables, LUTs) and eight storage elements. These elements are used by all slices to provide logic and ROM functions (Table 1). SLICEX is the basic slice. Some slices, called SLICELs, also contain an arithmetic carry structure that can be concatenated vertically up through the slice column, and wide- function multiplexers. The SLICEMs contain the carry structure and multiplexers, and add the ability to use the LUTs as 64-bit distributed RAM and as variable-length shift registers (maximum 32-bit). For more information see Spartan-6 FPGA Configurable Logic Block User Guide.
One single slice
One single LUT
The function generators in Spartan-6 FPGAs are implemented as six-input look-up tables (LUTs). There are six independent inputs (A inputs - A1 to A6) and two independent outputs (O5 and O6) for each of the four function generators in a slice (A, B, C, and D). The function generators can implement any arbitrarily defined six-input Boolean function. Each function generator can also implement two arbitrarily defined five-input Boolean functions, as long as these two functions share common inputs. Only the O6 output of the function generator is used when a six-input function is implemented. Both O5 and O6 are used for each of the five-input function generators implemented.
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