New Horizons









Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.



Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
Introduction
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard
Lab2. Booting from SD card and SPI flash
Lab2. PetaLinux board bringup
Lab2. Writing userspace IO device driver
Lab2. Hardware debugging
MicroZed quick start
Installing Vivado 2014.1
Lab3. Adding push buttons to our Zynq system
Lab3. Adding an interrupt service routine
Installing Ubuntu 14.04
Installing Vivado and Petalinux 2014.2

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

Linux
Installing Cobra Command Tool
A processor benchmark

Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Running
The New York City Marathon

Skiing/Skating
Kittelfjall Lappland

Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Wednesday, August 20, 2014
What's New
2014-08-20 Restarting my blog
2014-07-18 Vacation time. No access to ZedBoard
2014-05-20 As you can see to the left, there is an advertisement added to my blog. Please contact me if your company would like to place an ad at the same place.
2014-05-18 I am going social. Share buttons have been added to Facebook, LinkedIn, Twitter and Google social networking sites.
2014-05-06 Clive Maxfield at EE Times writes about my blog once more.
2014-03-15 The Zynq blog has been added to the Xilinx Wiki.
2014-03-13 A link to my Zynq blog has been added in ZedBoard.org
2014-03-11 I have written an article for EE Times about my Zynq blog
2014-02-18 Xilinx writes about my Zynq blog
2014-02-10 ElektronikTidningen writes about my Zynq blog (in Swedish)
2014-02-06 Starting a new blog called "Zynq Design From Scratch"
2014-01-14 Updated wildskating.com


Posted at 07:26 by svenand
Comments (4)  

 
Tuesday, August 19, 2014
Zynq design from scratch. Part 1.
Introduction

Almost a year ago I received a parcel by post from US. When I opened the parcel I found this box.




The ZedBoard was a present from someone involved in promoting the new Zynq device from Xilinx, but with no strings attached. At that time I was busy working as an ASIC designer and had no time to play with the board. It wasn't until December in 2013 that I had a chance to unpack the box and power-up the ZedBoard.

At that time I got an email from Per and Andreas at  Silica (Avnet) here in Stockholm, where they offered a one day hands-on training class on the Zynq-7000 using the ZedBoard, part of the "Xilinx Speedway Design Workshops". Here is what this workshop covered:

Introduction to the Zynq-7000 in Vivado AP SoC

"This class demonstrates the techniques and tools used to create a basic Zynq-7000 AP SoC design. Through a series of instructor presentations and hands-on labs, hardware and firmware developers will learn the required steps for creating a complete Zynq-7000 AP SoC design on ZedBoard. The Zynq-7000 AP SoC architecture is explained, including the ARM® Cortex™-A9 processing system (PS) and the 7 series programmable logic (PL). The course also details the individual components that comprise the PS such as I/O peripherals, clocking, interrupt, AXI interfaces and memory controllers. Emphasis will be placed on efficient PL-to-PS interfacing including processing interrupts generated from a PL peripheral. To complete the design flow, the critical steps of hardware and software debugging techniques will be shown".

This training session was the head start I needed. I went home and started to play with my ZedBoard. At the same time a decided to write this blog and here we are. All of you who have read my "FPGA design from scratch" blog will feel at home. I will follow the same idea and describe the whole design flow in an easy to understand fashion.

Reading instruction

Blog entries should be read from 1 onwards in numerical order to get the full story. At the end of every blog entry there are three links called:   Top   Previous  Next

  • Top takes us to the top of the current blog entry.
  • Previous takes us to the previous entry
  • Next takes us to the next entry 

Table of content

In the left sidebar there is a clickable TOC where you can access all blog entries:


Learning by doing

Aristotle once said, "For the things we have to learn before we can do them, we learn by doing them". So true. Let's practice some learning by doing.

Not reinventing the wheel

We will use a lot of material already available from Xilinx, Avnet and other companies. We will  try to find solutions to our problems by searching on internet.

A picture is worth a thousand words

I will use a lot of pictures in my blog. I think picture many times illustrates much better what is going on in my experiments.

An interactive meeting place

A would like the blog to be interactive and not a one-way document. I invite all of you,
newbies to professionals to ask questions, make comments and suggestions for subjects you are missing.

Acknowledgement

It wouldn't make sense writing a tutorial like this and not using Avnet's and Xilinx's in-depth knowledge about their products found in their web pages, user guides and other documents. I would like to thank Avnet and Xilinx for allowing me to use images and text from their documents and to link to their web pages.


Documentation

Here is a link to the Xilinx
documentation library.

E-Learning

Xilinx provides recorded
E-Learning for courses at our convenience. They are available at no charge.

Forums

There are several forums discussing FPGA design. The Xilinx forum is one of them. The Avnet forum and ZedBoard forum are two others.


Publications

Subscribe for FREE to the new Xcell Journal Digital. Here are links to old XCell magazines.

Search engines

There are a number of dedicated search engines, searching for FPGA information.
FPGASeek is one ChipHit is another.

Support, Answers Database

You may find an answer to your question in the
Xilinx support page.

Training

Xilinx provides targeted, high-quality education services designed by experts in programmable logic design, and delivered by Xilinx-qualified trainers. They offer instructor-led classes (both in person and online) and recorded e-learning for self-paced training. Some courses are completely free!  Doulos is running a 3 days course called "ARM Cortex-A9 for Zynq System Design".

WebCase

To post a question to Xilinx you should use
WebCase.

Wiki

The goal of the Xilinx Wiki site is to provide technical information and collaborate with the community on Open Source projects that are being done in Xilinx. Xilinx also provides a Git repository to help with open source development and collaboration, and all sources can be downloaded from the GIT repository

Xcell Daily Blog

Here is Xilinx own blog, Xcell Daily Blog.

Xilinx University Program


The Xilinx University Program (XUP) includes academics from top-tiered universities across the world. XUP provides top-quality teaching materials that are easily accessible to professors to incorporate into their curriculum. XUP offers workshops to professors and academic staff at no cost. These workshops are conducted by Xilinx as well as application area experts, providing in-depth practical and theoretical aspect of FPGA technology.


What to expect from this blog

You are welcome to follow my blog. I hope it will give you a head start in using the Zynq-7000 All Programmable SoC. Here is what I plan to do first.

  1. Select a computer to use. In my case a MacBook Air
  2. Setup a virtual machine using VirtualBox.
  3. Install Ubuntu Linux 13.10 64bit in the virtual machine
  4. Install Xilinx Vivado Design Suite (the Linux version)
  5. Use the Vivado software to generate a configuration bitstream
  6. Use Vivado SDK to write a simple program
  7. Connect the ZedBoard to the computer
  8. Configure the Zynq FPGA part and load the program
  9. Run the program that will light up some LEDs on the board


Just one last thing

We are going to have fun.






This time you are not left alone. Click Next to continue reading.

Top   Previous   Next


Posted at 11:50 by svenand
Comments (4)  

 
Monday, August 18, 2014
Zynq design from scratch. Part 49.
Installing Vivado 2014.2 and PetaLinux 2014.2

Xilinx has released new versions of Vivado and PetaLinux. Let's download and install the new releases and use them in a new project.

Download and install Vivado 2014.2

This time we will use the Web Install Client, a small program that can be downloaded from the Xilinx download page. Here is a video you can watch to learn more about the new download program.





Click the "Linux 64-bit Web Install Client" link.





Click Save File. The file will be downloaded to the Download directory if we haven't specified another directory. Make the file executable and and run it using sudo.





This will start the Xilinx Vivado installer.





Enter User ID and Password and click Next.





Accept the license agreements.





Select what to download.





Customize the installation by adding thing we need and remove things we don't need.





Look at the download size. Only 2.59 GB. Select destination directory.





See part 45 for the rest of the installation.

Installing Petalinux

We will follow the description in part 22 and install Petalinux 2014.2.








Download Board Support Package





Running the installer


Make the installer executable.

-> chmod 755 petalinux-v2014.2-final-installer.run

-> sudo ./petalinux-v2014.2-final-installer.run /opt/PetaLinux




Setup Vivado and PetaLinux SDK working environment

To setup the working environment we source the setup scripts:

-> source /opt/Xilinx/Vivado/2014.2/settings64.sh
-> source /opt/Xilinx/SDK/2014.2/settings64.sh
-> source /opt/PetaLinux/petalinux-v2014.2-final/settings.sh


Run the BSP install script


To install the board support packages we run the following commands:

-> cd $HOME/Projects/PetaLinux
-> petalinux-create -t project -s /home/svenand/Downloads/avnet-digilent-Zedboard-v2014.2-final.bsp


Now we are ready to load and boot PetaLinux on our ZedBoard. See part 23.

To rebuild the linux kernel see part 25.

Make sure you have installed the following libraries before building a new kernel.

  • lib32gomp1
  • lib32ncursesw5


Top   Previous   Next


Posted at 21:39 by svenand
Comment (1)  

 
Thursday, June 05, 2014
Zynq design from scratch. Part 48.
Measuring Linux usage

I know it is impossible to measure and figure out the real usage of different Linux distributions, but there is data collected from the web that can give us some clues. RedMonk has put together the following graph taking data from different sources.




After studying these figures and looking around in my neighbourhood I think one thing is clear. Debian together with its derivatives (Ubuntu and Mint) is by far the most popular Linux distribution in the world.


Xilinx Linux support




So why is Xilinx not supporting Debian? I don't know. But this doesn't stop us from using Ubuntu to run Xilinx software. I have been doing it since 2007 when I started using Xilinx design tools and continued up until today. So let's install Ubuntu 14.04.



Installing Ubuntu 14.04 LTS

The latest version of the Ubuntu operating system for desktop PCs and laptops, Ubuntu 14.04 LTS comes with five years of security and maintenance updates, guaranteed.






Follow the instructions in part 5 to install Ubuntu.
Yes it is that easy.


Fixing Ubuntu

Folllow the instructions in part 6 to perform the necessary fixes to make the Vivado run smoothly.

Installing Vivado

Follow the instructions in part 7 and part 45 to install Vivado and SDK and you are up a running in no time at all.

Top  Previous  Next



Posted at 09:36 by svenand
Make a comment  

 
Sunday, May 18, 2014
Zynq design from scratch. Part 47.
LED_Pushbuttons application program


Starting Xilinx SDK


--> xsdk &

Re-generate BSP sources

After we have modified our hardware design and added the interrupt logic we need to re-generate the Board Support Package to incorporate support for interrupts. Open the system.mss file, if not already opened and click Re-generate BSP Sources.





Create a new application program


We will keep the LED_Dimmer application as is and create a new application called LED_Pushbuttons.





Writing the program


We will use the LED_Dimmer c-program as a starting point and add support for push buttons and add an Interrupt Service Routine (ISR).

Not reinventing the wheel

Let's find some good examples that can help us implement the interrupt handling in our application. Open system.mss and click on examples for the axi_gpio_0 peripheral.





We will take a closer look at the xgpio_intr_example.c file.






My implementation


This is what I came up with. Take a look. Let's compile and run the program.  See part 19 for more information.





Here is the result.




Top   Previous   Next


Posted at 16:18 by svenand
Comments (3)  

 
Saturday, May 17, 2014
Zynq design from scratch. Part 46.
Adding push buttons and interrupts

This tutorial demonstrates how to modify our Zynq system from lab2 by adding inputs to the custom PL peripheral and connecting them to PS interrupts. This lab will show how to:

  • Modify the project's existing PS and PL subsystems
  • Update the C application for new hardware
  • Add interrupt handler and interrupt service routine (ISR)
  • Download and test the software application in hardware
1. We will use Vivado 2014.1 to build our new system.

--> vivado &





2. Open the LED_Controller project.





3. Expand system_wrapper in the Sources pane and double-click system_I -system (system.bd) to open Block Design. This is the new 2014.1 look.





4. Start to configure the AXI GPIO block by double-clicking the IP.

5. The Re-Customize IP window opens showing the AXI GPIO. Select the IP Configuration tab and check the setting for Enable Dual Channel. Set the GPIO 2 to All Inputs with GPIO Width 5. Check the setting for Enable Interrupt as well. Click OK.






6. Start to configure the PS block by double-clicking ZYNQ7 Processing System.

7. The Re-Customize IP window opens showing the ZYNQ Block Design.

8. We will start by adding a low speed clock (FCLK_CLK1) running at 250KHz and clocking the debounce circuit. Select Clock Configuration from the Page Navigator.





9. Before we can connect the interrupt signal we need to enable interrupts in the PS. Select Interrupts in the Page Navigator pane to the left and expand Fabric Interrupts and PL-PS Interrupt Ports. Enable Fabric Interrupts and IRQ_F2P[15:0]. Click OK.





10. Make a connection from ip2intc_irpt to IRQ_FP2[0:0] by holding down the left mouse button on one of the pins and draw a line to the other pin while still holding the button. The pointer should turn into a pen when the connection is made. A green check mark will show up at pins that are possible end points. Here is the connection made.




12. We also need to create external connections for the second GPIO channel that we can hook up to the rest of the logic in the PL. Right-click on the gpio2 interface symbol on the AXI GPIO block and select Make External. Select the gpio2 port symbol and rename the external interface from gpio2 to Pushbuttons in the External Interface Properties.





12. Here is the result.






13. Make the FCLK_CLK1 an external signal.





14. Improve the appearance by selecting Regenerate Layout and verify the connectivity by clicking Validate Design.

15. Save the Block Design by clicking Ctrl-S.


We have now added both an interrupt signal and an external port to the AXI GPIO. The interrupt signal has already been connected internally in the block design but the second gpio port is external to the block design. In the next part we will connect it to a HDL module.

Adding push buttons

We will modify and add HDL sources to connect the push buttons. When connecting pushbuttons, it is wise to debounce the signals. We will import a HDL module describing a debounce circuit circuit and connect the push buttons through it.

1. Since we have modified the block design we need to regenerate the HDL files that are required for implementation, simulation and synthesis. Expand Design Sources and system_wrapper (system_wrapper.v) in the Sources pane, right-click system(system.bd) and select Generate Output products. Click Generate.





2. Next we need to import the new HDL module that will debounce the pushbutton signals. We have already added a 250KHz clock from the PS that will be used to clock the debounce circuit and capture the pushbutton signals. The Verilog file debouncer.v can be downloaded from here (new version 2014-05-28).


3. To add the debouncer.v file to our design in the Flow Navigator pane select Project Manager->Add Sources.






4. Find and add the debouncer.v file.





5. Make sure that the box for Copy source into project is ticked and click Finish.


Modify the system_wrapper.v file


We need to modify the system_wrapper.v file to add our new debounce module. Double-click the system_wrapper.v file in the Design Source pane to open it in the Editor pane. We will make the following modifications:

  • Add an instantiation of the the debounce circuitry.
  • Add the FCLK_CLK1 signal
  • Connect clock, input and outputs to the rest of the system
  • Add a new input for the push buttons.
  • Connect debounce signals to the PROBE output
Save system_wrapper.v by typing ctrl-S. Here is the modified system_wrapper.v file (new version 2014-05-28).

RTL analysis

To get a graphical representation of our RTL code select RTL Analysis and click "Open Elaborated Design".










Synthesize the design

We need to clarify which external package pins that should be used to connect the input signals from the pushbuttons on the PCB. In order for Vivado to pick up all the signal names the design needs to be synthesized before I/O planning layout can be performed.

1. In the Flow Navigator pane, select Synthesis->Run Synthesis. The synthesis will take a few minutes to complete. Ignore any warnings. If we get an error we have to go back and check our design. Hopefully we get this message.





2. Change to Open Synthezised Design and click OK.


Connect package pins and implement the design


There are five push buttons connected to the PL. They are found here.





They are connected to the following package pins on the Zynq device.




3. Change to I/O planning layout in the toolbar. Follow the instructions in part 18 and add the five push buttons. Here is the result.





Generate bitstream

After fixing the package pins we are ready to generate a new bitstream file.

4. In the Flow Navigator pane, select Program and Debug->Generate Bitstream. Click Yes to run implementation. This will take a few minutes to complete. Ignore and close any warnings. When completed this window will be displayed.





5. Click OK to Open the Implemented Design. Must be open for exporting the bitstream file.



Export to SDK

6. Select File->Export->Export Hardware for SDK





Make sure to include the bitstream and click OK.





This completes the hardware session. In the next part we will add interrupt handling to our C application.


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Posted at 20:25 by svenand
Comments (5)  

 
Monday, May 05, 2014
Zynq design from scratch. Part 45.
Installing Vivado 2014.1 and SDK 2014.1

A few weeks ago Xilinx released Vivado 2014.1 and SDK 2014.1 Let's install them and find out if anything has changed and what is new. Here are the release notes.


Documentation

We can find all the documentation on the Xilinx support page. The first thing to read is the "Vivado Design Suite User Guide Getting Started". For more information see the following documents:
  • Vivado Design User Guide: Design Flows Overview (UG892)
  • Vivado Design User Guide: Embedded Processor Hardware Design (UG898)
  • Vivado Design Suite Tutorial: Embedded Hardware Design (UG940)
  • Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)
  • Vivado Design Suite User Guide: Using the Vivado IDE (UG893)
  • Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Installation

We will follow the instructions in part7 and only document things that have changed.

1.Download Xilinx_Vivado_SDK_Lin_2014.1_0405_1.tar.gz





2. Unzip, unpack and start the installer.





3. Select Vivado WebPACK.





4. Add the Software Development Kit (SDK)









5. Start the installation.





6. Here is the final result.





Edit .bashrc

We will add the following lines to the .bashrc file:





Licensing

For new purchases of the Vivado Licenses beginning in 2014.1, Vivado Licenses use an activation-based licensing scheme. Activation-based licensing offers robust security and return features, as well as pave the way for future licensing enhancements. For more information see the Vivado release notes (chapter 5).

Activation based licenses

Instead of requiring a file to be present to authorize a machine, Activation uses a trusted area on the client or server’s hard-drive to store the authorization credentials. This trusted storage area will automatically be installed and initialized beginning with the Vivado 2014.1 installer. When the Vivado tools look for a license feature, they are allowed to run if this trusted storage area contains the proper authorization.

License compatibility

Both certificate and activation-based licenses will be recognized by Vivado 2014.1 and later versions. If the license versions and dates are valid for the tool version being used, it does not matter whether the license is certificate or activation-based. For example, a certificate-based license issued during a previous Vivado release, which is still within the 1-year subscription period will authorize Vivado 2014.1 or later software. No conversion to a new license methodology will be necessary during the remainder of a previous subscription period.


Getting a new license file


Although we can continue using our old license file I see some advantages using an activation based license. Let's get one. Follow the instructions in part 7 to generate and download a new license file. This time we select an activation based license.





After generating the license file, it is downloaded to our $HOME/Download directory. The file is called Xilinx.lic and looks like this.





To me it looks like an XML file. Let's rename it to Xilinx.xml.


Using the Vivado License Manager

The Vivado License Manager is provided on computers with the Xilinx Vivado tools loaded. Use the command vlm to start the license manager.

-> vlm

1. Select Load Design.





3. Click "Activate License" and find the license file (Xliinx.xml).





4. Click Open to load the XML file to the trusted storage area.


Starting Vivado


-> vivado &


Here is the new start up window.





If you get a segmentation error when starting Vivado see part 8 for an explanation.


Starting SDK


-> xsdk &





We are ready to use the Vivado 2014.1 release. I have rerun lab1 and lab2 without any major problems. Almost everything worked as expected. Here are two small hiccups.

1. When starting Vivado the following errors were reported.





Easily fixed by changing the permissions for the 2014.1 directory.

-> sudo chmod 777 $HOME/.Xilinx/Vivado/2014.1

2. When running an application in SDK the following window was displayed.





Easily fixed by deleting the run configuration and creating a new one.

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Posted at 17:54 by svenand
Comments (8)  

 
Sunday, May 04, 2014
Zynq design from scratch. Part 44.
MicroZed

Time for a new suprise. Once again a parcel arrived and when unpacking it I found this box.





When opening the box I found the MicroZed board.






MicroZed™ is a low-cost development board based on the Xilinx Zynq®-7000 All Programmable SoC. Its unique design allows it to be used as both a stand-alone evaluation board for basic SoC experimentation, or combined with a carrier card as an embeddable system-on-module (SOM). MicroZed contains two I/O headers that provide connection to two I/O banks on the programmable logic (PL) side of the Zynq®-7000 AP SoC device. In stand-alone mode, these 100 PL I/O are inactive. When plugged into a carrier card, the I/O are accessible in a manner defined by the carrier card design.

The carrier card




Documentation

All the documentation can be found at the zedboard.org website.


MicroZed overview





Quick start


The MicroZed board comes with a pre-installed Linux image stored on the SPI flash. When we power up the board the Linux OS will boot automatically. Here is what we have to do.

The microSD card

The MicoZed board has a holder for a microSD card. When inserted during boot up the card will be mounted under /mnt. This means that we can install programs on the SD card from our Ubuntu host that can then be executed from the Linux installation running on the MicroZed.





Copy files to the microSD


We insert the microSD into the adapter and put it in our SD card reader/writer. For more information about connecting to the Ubuntu host see part 38.


We will add a bin directory and copy the PrimeNumber application to the microSD card.





Preparations

1. Verify the MicroZed boot mode (JP3-JP1) jumpers are set to QSPI card mode.




2. Connect an ethernet cable between the board and the ethernet switch.

3. Connect an USB cable between the board and the host computer. This cable connects  both power (+5V) and the terminal.





Terminal setup


We will use GTKterm as console. Start GTKterm in the Ubuntu guest OS (see part 14).

-> gtkterm &

Select port and set baud rate to 115200.





If everything works as expected we will see the zynq prompt in the console window.





Ethernet connection

We will change the MicroZed IP address to the same subnet as the rest of our system.





Now we can ping the board from our host computer.




FPGA configuration

Compared to the ZedBoard, the MicroZed does not have built-in USB-JTAG circuitry. There is a standard Xilinx PC4 connector for use with an external cable. Digilent has two JTAG programming cables we can use (HS1 and HS2). I will use the HS1 JTAG programming cable.





Install Digilent Adept JTAG drivers

Xilinx uses software from Digilent to configure Xilinx logic devices, initialize scan chains, program FPGAs, CLPDs and PROM. We will go to the Digilent web page and download all software from there. I know that some of this software is hidden somewhere in the SDK installation (/opt/Xilinx/SDK/2013.4/data/xicom/cable_drivers) but I prefer to do this installation from scratch and try to understand what is going on. For more information see part 13.


Connect to MicroZed board

We connect the programming cable between the PC4 connector and the USB port on our host computer.

PC4 connector
 








Jumper settings

We set the jumpers to cascaded JTAG chain.





VirtualBox settings

To make sure the USB device is recognized by our Ubuntu guest we open the VirtualBox settings and add the new USB device (Digilent Adept USB Device [0700].






After rebooting Ubuntu we can use the following commands to see if we have a working connection with the MicroZed board.





JTAG interface

You may wonder why there are two devices found. Here is the explanation.
The Zynq-7000 family of AP SoC devices provides debug access via a standard JTAG (IEEE 1149.1) debug interface. Internally, the AP SoC device implements both an ARM debug access port (DAP) inside the Processing System (PS) as well as a standard JTAG test access port (TAP) controller inside the Programmable Logic (PL). The ARM DAP as part of ARM CoreSight debug architecture allows the user to leverage industry standard third-party debug tools. For more information see the Zynq-7000 Technical Reference Manual (chapter 27).


Summary


This is all I planned to say about MicroZed for the moment. Most of the work we have done using ZedBoard can easily be transferred to MicroZed. Good luck!


Want to know more


For all of you using the MicroZeb board I recommend Adam Taylor's blog:
"Bringing up the Avnet MicroZed with Vivado".



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Posted at 16:50 by svenand
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Saturday, May 03, 2014
Zynq design from scratch. Part 43.
Hardware debugging

When you read this blog it may look like everything just works, but that is not always the case. I have spent many hours trying to understand what is going on inside my ZedBoard. For software debugging we have full access to almost all internal registers and can read and write to memory and set breakpoints and single step our programs. When it comes to hardware debugging we are much more restricted. Let's start by studying the document: "Vivado Design Suite User Guide, Programming and debugging"


Introduction

Debugging an FPGA design is a multistep, iterative process. Like most complex problems, it is best to break the FPGA design debugging process down into smaller parts by focusing on getting smaller sections of the design working one at a time rather than trying to get the whole design to work at once. Iterating through the design flow by adding one module at a time and getting it to function properly in the context of the whole design is one example of a proven design and debug methodology. We can use this design and debug methodology in any combination of the following design flow stages
.

  • RTL-level design simulation
  • Post-implemented design simulation
  • In-system debugging
  • Using external instruments


RTL design simulation

The design can be functionally debugged during the simulation verification process. Xilinx provides a full design simulation feature in the Vivado® IDE. The Vivado design simulator can be used to perform RTL simulation of our design. The benefits of debugging our design in an RTL simulation environment include full visibility of the entire design and ability to quickly iterate through the design/debug cycle. The limitations of debugging our design using RTL simulation includes the difficulty of simulating larger designs in a reasonable amount of time in addition to the difficulty of accurately simulating the actual system environment. For more information about using the Vivado simulator, refer to the Vivado Design Suite User Guide: Logic Simulation (UG937)


Post-implemented design simulation

The Vivado simulator can also be used to simulate the post-implemented design. One of the benefits of debugging the post-implemented design using the Vivado simulator includes having access to a timing-accurate model for the design. The limitations of performing post-implemented design simulation include those mentioned in the previous section: long run-times and system model accuracy.


In-system logic design debugging

The Vivado IDE also includes a logic analysis feature that enables us to perform in-system debugging of the post-implemented design an FPGA device. The benefits for debugging our design in-system include debugging our timing-accurate, post-implemented design in the actual system environment at system speeds. The limitations of in-system debugging includes somewhat lower visibility of debug signals compared to using simulation models and potentially longer design/implementation/debug iterations, depending on the size and complexity of the design.


ChipScope Pro and the Serial I/O toolkit

ChipScope™ Pro tool inserts logic analyzer, system analyzer, and virtual I/O low-profile software cores directly into our design, allowing us to view any internal signal or node, including embedded hard or soft processors. Signals are captured in the system at the speed of operation and brought out through the programming interface, freeing up pins for your design. Captured signals are then displayed and analyzed using the ChipScope Pro Analyzer tool.

The ChipScope Pro Serial I/O Toolkit provides a fast, easy, and interactive setup and debug of serial I/O channels in high-speed FPGA designs. The ChipScope Pro Serial I/O Toolkit allows us to take bit-error ratio (BER) measurements on multiple channels and adjust high-speed serial transceiver parameters in real-time while your serial I/O channels interact with the rest of the system. To use ChipScope Pro we need a seperate license not included in Vivado WebPACK.


Debugging using external instruments

The possibility to analyze what is going on inside our Zynq device is valuable, but when we want to measure what is happening on our ZedBoard, we have to rely on external instrumentation. Professional logic analyzers and oscilloscopes are expensive instruments (>$1000) and maybe not reachable for our hobby projects. Let's look for a cheaper solution. When looking around I found LogiScope from Oscium.


LogiScope logic analyzer

LogiScope transforms an iPhone, iPad or iPod into a 100MHz, 16 channel logic analyzer. Not only is it the most intuitive logic analyzer available, the triggering is so powerful we'll be able to count the hair on our bugs (not my words). Specifications:

  • 100 MHz, 16 channel logic analyzer
  • Two logic harnesses (each with 8 digital, 1 ground)
  • Protocol decoding: I2C, SPI, UART, Parallel
  • Record length : 1000
  • Maximum input bandwidth : 30MHz
  • Works with 2.0v, 2.5v, 3.3v & 5.0v systems
  • Portable: goes where you go
  • Input voltage -0.5v to +7v
  • Advanced triggering
  • Compatible with Lightning and 30 pin connectors (with adapter, works with iPhone 5 & iPad Mini
  • Price : $200 (€150)



Looks like a perfect instrument for our project. Let's order one. If you live in Europe you can order it from Lab eSHOP. In the rest of the world it can be ordered from the Oscium webpage.


Delivery

It took a few days and then this box appered on my desk.



Unpacking and connecting

Unpacking and connecting to the ZedBoard took only a few minutes. I have the first generation iPad which I used in my setup.



A closer look at the connection to the ZedBoard. As you can see I am using the Pmod connectors JA1 and JB1. The black wires are connected to ground.



Download and install

The iPad or iPhone app running the Logic Analyzer can be downloaded for free from the Apple AppStore (search for LogiScope).



Adding probes to the design

We have to modify our design to bring out the signals we would like to look at to the Pmod connectors. Here is a description on how to do that. 

1.Find out which Zynq pins are connected to the Pmod connectors. The information can be found in the ZedBoard Hardware Guide.

2. Start Vivado and open the LED_Controller project.

3. Open the system_wrapper.v file and add the PROBE output. We will connect the LEDS PWM signals and the FCLK_CLK0. The unused outputs will be forced to both 0 and 1.

 
    LEDS,
    PROBES
    );

   output [15:0] PROBES;

// Probes used for logic analyzer
   assign PROBES = {7'b1010101,FCLK_CLK0,LEDS};

4. Save the system_wrapper.v file (ctrl-S).

5. Follow the instructions in part 18 to synthesize the design and add new pin locations.

6. Connect the PROBE outputs to the Pmod connectors.


7. Run implementation and generate the new bitstream file.

8. Export design to SDK. Make sure the new bitstream file is exported.

9. Start SDK and connect to the new hardware design.

10. Follow the instructions in part 19 to load the new hardware design and to run the LED_Dimmer program.

11. Turn on the iPad and start the LogiScope app. Select different settings from the terminal and watch the pulse width changing.



To get started

Learn how to get started from this blog at EEweb.

Triggering demos

Oscium has put up three videos on their webpage illustrating the power of the advanced triggering system.

Conclusion

The LogiScope logic analyzer is very easy to setup and to use. It has its limitation when it comes to analyzing high-speed clocks > 30MHz but we can always add some prescaler logic in the programmable logic part before bringing out the signals. I think this instrument can be very useful in our Zynq design project.


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Posted at 21:02 by svenand
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Wednesday, April 30, 2014
Zynq design from scratch. Part 42.
Writing userspace IO device driver

UIO Drivers

Linux provides a standard called UIO (User I/O) framework for developing user-space-based device drivers. The UIO framework defines a small kernel-space component that performs two key tasks:

a.    Indicate device memory regions to user space.
b.    Register for device interrupts and provide interrupt indication to user space.

The kernel-space UIO component then exposes the device via a set of sysfs entries like /dev/uioXX. The user-space component searches for these entries, reads the device address ranges and maps them to user space memory.

The user-space component can perform all device-management tasks including I/O from the device. For interrupts however, it needs to perform a blocking read() on the device entry, which results in the kernel component putting the user-space application to sleep and waking it up once an interrupt is received.

Characteristics

If we use UIO for our card's driver, here's what we get:
  • only one small kernel module to write and maintain.
  • develop the main part of our driver in user space, with all the tools and libraries we're used to.
  • bugs in our driver won't crash the kernel.
  • updates of our driver can take place without recompiling the kernel.

Creating an UIO driver

In this section we will create an UIO driver using the UIO framework.  We will modify the program used in part41 and call it: LED_DimmerUIO.c.


1. We start by generating a new application called LED_DimmerUIO.

-> cd ..../PetaZed
-> petaliniux-create -t apps --name LED_DimmerUIO

2. Replace the template file LED_DimmerUIO.c with the file downloaded from this page.


Configure user application

3. Run petalinux-config -c rootfs and select the LED_DimmerUIO application.

-> petalinux-config -c rootfs



4. Save and exit

Configure the Linux kernel

5. Run petalinux-config -c to start kernel configuration

-> petalinux-config -c kernel

6. Scroll down and select Device Drivers.



7. Scroll down and select Userspace I/O drivers.



8. Mark with an "M" for module.



9. Save and exit.

Edit the system.dts file

We find the device tree definition file system.dts file here:



10. Open the system.dts file in an editor and change the line after #gpio-cells = <2> to compatible = "generic-uio";



Rebuild the Linux kernel

The first time after we added the UIO module and edited the DTS file we have to rebuild the kernel from scratch.

-> petalinux-build -x mrproper
-> petalinux-build

When the build has finished we copy the image.ub file to the SD card and we are ready to boot PetaLinux.

Boot PetaLinux

Insert the SD card, power on the board and connect a terminal. Here are the commands executed to load the UIO module:


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Posted at 13:31 by svenand
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